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Veepsa Bhatia
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In this paper a new current comparator architecture is presented, which utilizes the concept of nonlinear feedback to speed up the operation. The analytical formulation for quantifying the effect of the feedback is put forward. The functionality of the proposed comparator is verified using simulations carried out on an Orcad Pspice tool using Taiwan Semiconductors Manufacturing Company (TSMC) 0.18 µm technology parameters. The resolution and delay are found to be ± 10 nA and 1.48 ...
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Depok: Faculty of Engineering, Universitas Indonesia, 2016
UI-IJTECH 7:1 (2016)
Artikel Jurnal Universitas Indonesia Library
